The present invention relates in general to a data processing system, and in particular, to instruction prefetch in a data processing system.
As computers have been developed to perform a greater number of instructions at greater speeds, many types of architectures have been developed to optimize this process. For example, the reduced instruction set computer (RISC) device uses simpler instructions and greater parallelism in executing those instructions to ensure that computational results will be available more quickly than the results provided by more traditional data processing systems. In addition to providing increasingly parallel execution of instructions, some data processing systems employ memory devices within the processor to permit retrieval of instructions from a system memory before they are required for execution by the processor. A set of instructions is loaded from a system memory device into this processor memory, the so-called primary or level 1 (L1) cache for subsequent dispatching to execution units within the processor. The set of instructions loaded from memory includes a sufficient number of instructions to fill a block of cache memory of predetermined size, a xe2x80x9ccache line.xe2x80x9d
Fetching units first look to the cache for the next instruction it needs. If the instruction is not in the cache, a xe2x80x9ccache miss,xe2x80x9d the fetching unit must retrieve the instruction from the system memory, slowing down instruction processing. In such a cache miss, the cache fetches the requested instruction or data, and prefetches from memory sufficient succeeding instructions or data to fill the remaining locations in the cache line.
Thus, a cache line prefetch is delayed until the cache miss occurs. Then, a fixed number of instructions, or a fixed number of data words, enough to fill a single cache line, are prefetched from system memory. The number of instructions, or the amount of data, is predetermined, even if it is probable that, because of the software being executed, a subsequent instruction or data request will hit beyond the cache line boundary. This may diminish the reduction in memory latency that might otherwise be obtained if software participated in the prefetch process. Thus, there is a need in the art for a mechanism by which software may initiate the prefetch of data and instructions.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a mechanism for software hint initiated prefetch. The mechanism includes circuitry operable for issuing at least one prefetch request to one or more memory devices in response to a software instruction, the circuitry including at least one first register having a plurality of fields each operable for receiving a corresponding data value, each data value specifying a parameter for controlling the prefetch.
There is also provided, in a second form, a method of software hint initiated prefetch. The method includes the steps of storing a plurality of prefetch specifications in a register in response to a software instruction, and initiating a prefetch request for a cache line having an address corresponding to a first one of the plurality of prefetch specifications.
Additionally there is provided, in a third form, a data processing system for software hint initiated prefetch including at least one first memory device and at least one second memory device, and a data processor coupled to the at least one first and second memory devices. The data processor contains circuitry operable for issuing at least one prefetch request to the at least one first and second memory devices in response to a software instruction, the circuitry including at least one first register having a plurality of fields each operable for receiving a corresponding data value, each data value specifying a parameter for controlling the prefetch.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.